Espressif's shift from proprietary Xtensa cores to the open RISC-V instruction set architecture is now shipping silicon. The ESP32-S31, which entered mass production in late July 2026, pairs two 32-bit RISC-V application cores clocked at up to 320 MHz with a low-power 40 MHz RISC-V coprocessor. That is a meaningful step up from the ESP32-S3's dual Xtensa LX7 cores at 240 MHz, and the move to an open ISA means the broader toolchain ecosystem around GCC and LLVM for RISC-V continues to benefit. One of the high-performance cores includes a 128-bit data path with SIMD instructions, and Espressif's benchmarks put the dual-core configuration at 2195 CoreMark at 320 MHz.

The real appeal for anyone building connected devices is the protocol convergence. A single ESP32-S31 handles 2.4 GHz Wi-Fi 6 with OFDMA and MU-MIMO, Bluetooth 5.4 (both LE Audio and Classic), IEEE 802.15.4 for Zigbee 3.0 and Thread 1.4, and a Gigabit Ethernet MAC. That combination lets one chip act as a Matter bridge or smart-home hub over either Wi-Fi or Thread without requiring a separate radio module. Bluetooth Classic support, which Espressif dropped in some recent SoCs, is back here, keeping the door open for legacy audio and serial profiles.

On the memory and I/O side, the ESP32-S31 carries 512 KB of high-performance SRAM and supports up to 32 MB of in-package octal PSRAM over a 250 MHz DDR interface. GPIO count jumps to 60 pins (up from 45 on the S3), and the chip integrates a JPEG codec, a pixel-processing accelerator, dual I2S interfaces with hardware Bluetooth audio sync, DVP camera and LCD panel interfaces, and 14 capacitive-touch channels. The chip also includes a hardware MMU with sv32 paging, which distinguishes it from the vast majority of microcontrollers and makes it capable of hosting a full operating system kernel on-device. Security hardware covers AES, SHA, RSA, ECC, ECDSA, secure boot, and flash encryption.

Software support runs through Espressif's open-source ESP-IDF framework alongside ESP-Matter, ESP-BLE-MESH, ESP-BLE-AUDIO, and ESP-GMF for multimedia. The chip can also operate as a wireless coprocessor via ESP-Hosted or ESP-AT, which makes it useful as a connectivity add-on for Linux SBCs or other host processors that lack native wireless.

The MMU has already drawn community efforts to run Linux natively on the chip. GrieferPig's esp32-s31-linux project boots Linux 6.12 on the ESP32-S31-WROOM-3, with the primary obstacle being the chip's CLIC interrupt controller (the S31 uses a Core Local Interrupt Controller rather than the PLIC that standard Linux RISC-V ports expect), which required a custom driver. The chip's supervisor mode also departs from the RISC-V privileged specification in several respects, so much of that bring-up relied on CSR probing and cross-referencing Espressif's internal P4 technical reference. A separate project by annoyedmilk targets the Korvo-1 board and has reached Linux 7.1 with OpenSBI 1.9, using the octal PSRAM as a 16 MiB system memory pool. That port brings SD card access through the standard dw_mmc driver (the S31's SD host controller is a Synopsys DesignWare MSHC), USB host through the dwc2 driver with HID and evdev support for keyboards and mice, and FAT and ext4 filesystem access, along with a proof-of-concept framebuffer for the Korvo-1's 800x480 RGB LCD panel. Both projects are early-stage community work rather than upstream kernel support, but the clean mapping of standard Linux peripheral drivers onto the hardware's IP blocks is a promising foundation for future upstream submissions.

Two initial variants ship in an 8 x 8 mm QFN80 package rated from -40 to 85 degrees C: the ESP32-S31NRV16 with 16 MB PSRAM and the ESP32-S31NRV32 with 32 MB. The bare ESP32-S31NRV16 lists at roughly $4.50 (€4.15), while the ready-to-solder ESP32-S31-WROOM-3 module runs about $5.85 (€5.40).