AMD has unveiled the Kintex UltraScale+ Gen 2 FPGA family, a mid-range lineup targeting broadcast, test, industrial, and medical markets with a notable promise: availability through at least 2045. The announcement came at Integrated Systems Europe 2026, where AMD positioned the new chips as a modernization of its UltraScale+ architecture with faster memory, updated I/O, and post-quantum cryptography support.
The Gen 2 family spans three devices offering between 328K and 491K logic cells, with integrated LPDDR4X, LPDDR5, and LPDDR5X memory controllers. AMD claims up to 5x higher memory bandwidth compared to the previous generation Kintex UltraScale+ parts, and up to 2x the PCIe channel density versus competing Altera Agilex FPGAs. The top-end XC2KU050P packs 24 GTY transceivers running at 32.75 Gb/s, dual 100G CMAC blocks, and PCIe Gen4 interfaces upgraded from the Gen3 found in earlier chips. AMD has also baked in support for the NSA's Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) for post-quantum cryptography applications.
The FPGAs are designed for equipment requiring fast sensor inputs and strict latency, including 4K AV-over-IP systems, semiconductor test and inspection gear, machine vision platforms, and medical imaging equipment. AMD's engineering projections suggest up to 80% more embedded RAM and 2x the DSP density compared to Altera's Agilex A5EC052A, though these claims await independent verification.
Developers will need to wait before getting silicon in hand. Vivado and Vitis simulation support arrives in Q3 2026, with pre-production XC2KU050P samples shipping in Q4 2026 and mass production slated for H1 2027. An evaluation kit will also begin sampling in Q4 2026.
